1. Field of the Invention
The present invention relates to a DRAM having the multi-bank configuration and, particularly, a semiconductor memory device comprising a DRAM having a data register in a sense amplifier bank for performing late write.
2. Description of the Related Art
In a DRAM having a so-called multi-bank configuration including a plurality of memory banks, when continuously performing the operations of reading and writing, since write data latency and read data latency are different, it becomes necessary to insert an optional number of NOP instruction (standby instruction) to prevent data conflict of a data bus when shifting from reading to writing.
FIG. 7 is a block diagram of a configuration example of a multi-bank DRAM of the related art. As shown in FIG. 7, the multi-bank DRAM comprises an address latch circuit 100, a row decoder 110, a memory cell array 120, a column decoder 130, a column selector 140, a sense amplifier control circuit 150, a sense amplifier 160, a column address latency control circuit 170, a MA, LIO MUX control circuit 180, a bank address decoder 190, a multiface array timing generation circuit 200, a command decoder 210 and an input/output circuit 220.
Also, as shown in FIG. 7, the multi-bank DRAM of the present example is, for example, provided with four memory banks, that is, a bank A, a bank B, a bank C and bank D. In each memory bank, a row decoder 110, a memory cell array 120, a column decoder 130, a column selector 140, a sense amplifier control circuit 150 and a sense amplifier 160 are independently provided, respectively.
Below, each component of the multi-bank DRAM of the present example will be explained briefly.
The address latch circuit 100 holds an address ADR input from the outside and outputs the held address ADR to the row decoder 110, the column decoder 130, the column address latency control circuit 170 and the bank address decoder 190, respectively.
In each memory bank, in accordance with the input row address RADR, the row decoder 110 selects a word line specified by the row address RADR and activates the same.
The memory cell array 120 is configured by arranging a plurality of memory cells in a matrix. A word line is provided for each line of the matrix and a bit line is provided for each column. When accessing a memory cell array, the row decoder 110 selects a word line and the column selector 140 selects a bit line.
In accordance with the input column address CADR, the column decoder 130 generates a column selection signal and outputs it to the column selector 140.
The column selector 140 is provided with a plurality of column selection gates corresponding to the respective columns of the memory cell array. In accordance with a column selection signal output from the column decoder 130, a column selection gate corresponding to a column specified by the column address CADR is opened and a bit line of the selected column and a sense amplifier corresponding thereto are connected.
The sense amplifier control circuit 150 supplies a drive voltage to the sense amplifier 160 at a predetermined timing and controls an operation of the sense amplifier in accordance with control signals from the column address latency control circuit 170, the bank address decoder 190 and the multiface array timing generation circuit 200.
The sense amplifier 160 amplifies a potential difference of a bit line pair connected thereto and holds a voltage of an amplified bit line. When reading, the sense amplifier 160 amplifies the potential difference arisen in the bit line pair in accordance with memory data of a selected memory cell and outputs the amplification result to the outside so as to read out the stored data of the selected memory cell to the outside. On the other hand, when writing, the sense amplifier latches a voltage of the bit line pair in accordance with write data. In accordance with the latched bit line voltage, charges are stored in a capacitor of the selected memory cell.
The column address latency control circuit 170 generates a control signal to control a latency time of column accessing in accordance with an address ADR input from the address latch circuit 100 and outputs it to the sense amplifier control circuit 150 and the MA, LIO MUX control circuit 180.
The MA, LIO MUX control circuit 180 receives a column address and an MA control signal (WLIO write and read control signal) for selecting a set of WLIO from a plurality of WLIO for one main amplifier controlled by the column address latency control circuit 170 and performs a data transaction between the input/output circuit 220, the data register 290 and the sense amplifier 160.
The bank address decoder 190 generates a memory bank selection signal for selecting one memory bank from a plurality of memory banks in accordance with a bank address BADR input from the address latch circuit 100 and outputs it to the row decoder 110 and the column decoder 130 of the respective memory banks.
The multiface array timing generation circuit 200 generates a control signal for controlling operation timing at the time of memory accessing and outputs it to the row decoder 110 and the sense amplifier control circuit 150, respectively.
The command decoder 210 decodes a command CMD input from the outside, generates a read command RCMD and a write command WCMD in accordance therewith and outputs then to the bank address decoder 190.
The input/output circuit 220 holds write data DQ input from the outside and outputs the held write data to the MA, LIO MUX control circuit 180 via a data line WGIO when writing. While when reading, since data read from the selected memory cell by the sense amplifier 160 are output to the input/output circuit 220 via the MA, LIO MUX control circuit 180 and the data line WGIO, the input/output circuit 220 holds read data from the data line WGIO and outputs then to the outside.
FIG. 8A to FIG. 8J are timing charts when performing a writing, reading and writing operation on the same bank in a multi-bank DRAM of the related art. Below, the writing, reading and writing operations of the multi-bank DRAM of the related art will be explained with reference to FIG. 8A to FIG. 8J.
As shown in FIG. 8A to FIG. 8J, it is assumed that write data latency (latency time) is 0, read data latency is 4, an address input is low and no column multiplex. Furthermore, an array cycle time tRC is assumed to be a 4-clock cycle.
In the multi-bank DRAM in FIG. 8A to FIG. 8J, in memory accessing to the same bank, at least accessing to the same memory bank is controlled to be performed by waiting for the array cycle time tRC for preventing data destroy by an interruption of a series of refresh operation.
As shown in timing charts of FIG. 8A to FIG. 8J, a period of four cycles of a clock signal CLK from a time t0 is a write operation period (indicated by “W” in FIG. 8A to FIG. 8J), a 4-clock cycle from a time t4 is a read operation period in the same bank A (indicated by “R” in FIG. 8A to FIG. 8J), a 4-clock cycle from a time t8 is a NOP period (standby period) inserted for preventing conflict of data lines (indicated by “N” in FIG. 8A to FIG. 8J), and a 4-clock cycle from a time t13 is a next write operation period.
As shown in FIG. 8, write addresses A0, B0, C0 and D0 are input for every clock cycle in the write operation period (FIG. 8B). Also, write data dA0, dB0, dC0 and dD0 are successively input at the same time with the addresses (FIG. 8C).
In accordance with the input address, an address latched by the address latch circuit 100 is transferred to a common address bus shared by a plurality of memory banks (FIG. 8D).
As shown in FIG. 8E, a memory bank selected by the bank address, bank A here, is activated, and input write data dA0 is written to a selected memory cell in the bank A via the write common input/output circuit (WGIO) and a write data line WLIO/WLIOB.
Also in the same way, as shown in FIG. 8F to FIG. 8H, write data are successively transferred, such as the bank B at a time t1, the bank C at time t2 and the bank D at a time t3, and writing is performed on the memory cell specified by the respective banks by the write addresses.
In a read operation, similar to the write operation, a read address A1 is input to a common address bus at a time t4. Successively, read addresses B1, C1 and D1 are input to common address buses for each clock cycle.
At time t4, a read address A1 selected by a bank address is input, stored data are read from a memory cell specified by the address A1 in the bank A in accordance therewith, amplified by the sense amplifier, output from the bit line to read data lines RLIO and /RLIO, and furthermore output to the outside via the input/output circuit 220.
Continuously, from a time t5, the banks B, C and D are successively selected for each clock cycle, stored data are read from a memory cell selected by a read address input to each bank and successively output.
In the above multi-bank DRAM disclosed in Japanese Unexamined Patent Publication No. 3-273594, since the write latency is 0 and the read latency is 4, read data are not output until a point when the latency of four cycles of the clock signal CLK from the start of reading is past in a series of memory access operations of performing writing continuously from reading. Thus, when performing writing continuously from a reading operation, to prevent conflict of data on a common data bus, it is necessary to insert a standby time, that is, a NOP instruction corresponding to several cycles of the clock CLK.
By inserting the standby period between the read operation period and the write operation period, a state in which effective data do not exist on the common data bus appears at a certain frequency. Namely, the ratio of the time for transferring effective data on the data bus in the whole operation period is reduced, so that there arises a disadvantage that the utilization of the data bus declines or the effective data transfer rate of the data bus declines.